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PRELIMINARY
CY62148
512K x 8 Static RAM
Features
* 4.5V-5.5V operation * CMOS for optimum speed/power * Low active power -- 660 mW (max.) * Low standby power (L version) -- 2.75 mW (max.) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE options an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62148 is available in a standard 32 pin 450-mil-wide body width SOIC and 32 pin TSOP II packages.
Functional Description
The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has
Logic Block Diagram
Pin Configuration
Top View SOIC TSOP II
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
62148-2
I/O0
INPUT BUFFER
A0 A1 A4 A5 A6 A7 A12 A14 A16 A17
I/O1
ROW DECODER
I/O2
SENSE AMPS 512 x 256 x 8 ARRAY
I/O3 I/O4 I/O5
CE WE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A2 A3 A15 A18 A13 A8 A9 A11 A10
OE
62148-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 June 30, 1998
PRELIMINARY
Selection Guide
CY62148-55 Maximum Access Time (ns) Maximum Operating Current L LL Maximum CMOS Standby Current L Commercial Industrial
Shaded areas contain advance information.
CY62148
CY62148-70 70 120 90 90 2 mA 100 A 20 A 40 A
CY62148-100 100 120 90 90 2 mA 100 A 20 A 40 A
55 120 90 90 2 mA 100 A 20 A 40 A LL LL
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND........ -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage ..................................-0.5V to VCC +0.5V
[1]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 4.5V-5.5V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current GND VI V CC GND VI VCC, Output Disabled VCC = Max., IOUT + 0 mA, f = fMAX = 1/tRC L LL ISB1 Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs Max. VCC, CE VIH VIN V IH or VIN V IL, f = fMAX Max. VCC, CE VCC - 0.3V, VIN V CC - 0.3V, or VIN 0.3V, f=0 1.6 A L Com'l Ind'l LL LL 1.6 1.6 1.6 Test Conditions VCC = Min., IOH = - 1mA VCC = Min., IOL = 2.1mA 2.2 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 120 90 90 15 Typ.[3] Max. Unit V V V V A A mA mA mA mA
ISB2
2 100 20 40
mA A A A
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Typical values are measured at VCC = 5V, TA = 25C, and are included for reference only and are not tested or guaranteed.
2
PRELIMINARY
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8
CY62148
Unit pF pF
AC Test Loads and Waveforms
R1 1838 5V OUTPUT 5 pF R2 994 R1 1838 5V OUTPUT 5 pF R2 994 GND 3 ns 5.0V 90% 10% 90% 10% 3 ns
62148-5
ALL INPUT PULSES
INCLUDING INCLUDING JIG AND JIG AND SCOPE (b) 62148-3 (a) SCOPE Equivalent to: THEVENIN EQUIVALENT 645 1.75V OUTPUT
62148-4
Switching Characteristics[5] Over the Operating Range
62148-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[7] [6, 7]
62148-70 Min. 70 Max.
62148-100 Min. 100 Max. Unit ns 100 10 100 50 5 30 10 30 0 100 100 80 80 0 0 60 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 55
Max.
55 10 55 20 5 20 10 20 0 55 55 45 45 0 0 45 25 70 60 60 0 0 55 25 0 10 5 10
70 70 35 25 25 70
OE HIGH to High Z CE HIGH to High Z
CE LOW to Low Z[7]
[6, 7]
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End
WRITE CYCLE[8]
Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 100-pF load capacitance. 6. t HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
Switching Characteristics[5] Over the Operating Range (continued)
62148-55 Parameter tHD tLZWE tHZWE WE HIGH to Low Z Description Data Hold from Write End
[7]
CY62148
62148-70 Min. 0 5 Max.
62148-100 Min. 0 5 Max. Unit ns ns 30 ns
Min. 0 5
Max.
WE LOW to High Z[6, 7]
20
25
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Com'l L LL Ind'l tCDR[4] tR Operation Recovery Time LL Chip Deselect to Data Retention Time No input may exceed VCC + 0.3V VCC = VDR = 3.0V CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V Conditions Min. 2.0 1.6 A 1.7 80 20 40 0 tRC Typ.[2] Max. Unit V mA A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
62148-6
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No.1 [9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
62148-7
Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle.
4
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[10, 11]
CY62148
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
62148-8
HIGH IMPEDANCE
Write Cycle No. 1 (CE Controlled)[12, 13]
tWC ADDRESS tSCE CE tSA
tAW tPWE WE tSD DATA I/O DATA VALID tHD
tHA
62148-9
Notes: 11. Address valid prior to or coincident with CE transition LOW. 12. Data I/O is high-impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
tWC ADDRESS tSCE CE
CY62148
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 14 tHZOE DATAIN VALID
62148-10
tHD
Write Cycle No.3 (WE Controlled, OE LOW)
[12, 13]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATAI/O NOTE 14 tHZWE
Note: 14. During this period the I/Os are in the output state and input signals should not be applied.
tHA tPWE
tHD
DATA VALID tLZWE
62148-11
6
PRELIMINARY
Truth Table
CE H L L L OE X L X H WE X H L H I/O0 - I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode
CY62148
Power Standby (ISB) Standby (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 70 Ordering Code CY62148-70SC CY62148-70ZSC CY62148L-70SC CY62148L-70ZSC CY62148LL-70SC CY62148LL-70ZSC CY62148-70SI CY62148-70ZSI CY62148L-70SI CY62148L-70ZSI CY62148LL-70SI CY62148LL-70ZSI 100 CY62148-100SC CY62148-100ZSC CY62148L-100SC CY62148L-100ZSC CY62148LL-100ZSC CY62148LL-100ZSC CY62148-100SI CY62148-100ZSI CY62148L-100SI CY62148L-100ZSI CY62148LL-100SI CY62148LL-100ZSI Document #: 38-00564 Package Name S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 S34 ZS32 Package Type 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP II Industrial Operating Range Commercial
7
PRELIMINARY
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
CY62148
51-85081-A
8
PRELIMINARY
Package Diagrams (continued)
32-Lead TSOP II ZS32
CY62148
51-85095
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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